The present invention relates to digital computer systems. More particularly, it relates to memory write amplifiers for such computer systems.
In computer systems, there are numerous uses for random access memories (RAMs). For example, a computer system includes one or more central processor units (CPUs), each of which may include at least one cache memory. Cache memories are used as a temporary store for blocks of data most used by the associated CPU. They provide a rapid access to the stored data which otherwise must be manipulated by accessing the much slower main memory. In a co-pending patent application, referenced herein above, there is described a memory unit which may be accessed during each half cycle of the controlling clock signal. The memory unit may be accessed for writing during a particular half cycle or it may be accessed for reading during either or both half cycles of the clock signal. In conventional arrangements, output signals from the write amplifier controls the write cycle to write into the addressed memory cell a polarized signal in accordance with an applied data signal. Separate means are provided for establishing a read cycle for the addressed memory cell.